IBM Unveils World's First 0.7nm Chip, Packing Nearly 100 Billion Transistors Onto a Fingernail-Sized Die
The world's first sub-1 nanometer logic chip
For over 40 years, chips have advanced by shrinking transistors smaller and smaller — now the size is closing in on a single atom. This is the first time the industry has crossed below 1 nanometer, and IBM's method isn't more shrinking — it's stacking transistors vertically instead.
- IBM announced the world's first sub-1nm chip technology, naming the node 0.7 nanometer (7 angstrom) — a fingernail-sized chip integrating nearly 100 billion transistors, roughly double the density of a 2021 2nm chip.
- The core innovation is a new transistor architecture called nanostack: instead of shrinking the 2D footprint, transistors are stacked and staggered in 3D — the industry's first three-dimensional nanosheet architecture.
- Three key techniques: stacking + staggering, 3D sequential integration, and independently optimized materials per layer.
- Already validated as manufacturable via experiments including a functional CMOS inverter; the +50% performance or +70% efficiency figures are projections relative to 2nm, and it's one or the other, not both.
- Aimed at generative AI, cloud infrastructure, and next-gen devices; IBM says production could arrive within 5 years, with a roadmap extending at least a decade further.
To understand this breakthrough, first see how hard the wall really is
Crossing below 1 nanometer is a milestone because the old path was genuinely running out of road. For decades, chips got better through one straightforward move: make transistors smaller so more fit on the same chip, pushing compute and efficiency up together. The problem is transistor sizes are now approaching the scale of a single atom — there's barely any room left to keep shrinking on a flat plane. The "just make it smaller" path is nearly played out.
Instead of forcing more out of the old path, IBM switched dimensions this time: if there's no more room on the plane, go vertical. Click through the four steps below to see how it doubles transistor count in the same footprint.
The old way: transistors are laid out on a single plane, so getting more means shrinking each one further. But we've hit the "atomic wall" — there's not much room left to shrink.
Nanostack's first move: stack up, and offset the layers. A new layer of transistors is stacked above the original one, staggered relative to it (IBM calls this a staggered channel) — so the same footprint fits twice as many.
Second move: swap materials layer by layer. The upper layer of transistors can use a different material than the lower layer — each picks whatever suits it best, optimizing performance and power independently, without compromise. A flat architecture can't offer that.
Result: the same fingernail-sized chip now packs nearly 100 billion transistors, roughly double the density of a 2021 2nm chip.
Like turning a lot of single-story houses on a plot of land into staggered multi-story apartments: the footprint (chip area) stays the same, but stacking upward fits more residents (transistors), and each floor can even be fitted out differently (different materials).
How did IBM actually pull this off: the three moves behind nanostack
Stack transistors vertically — and stagger them
In a traditional architecture, transistors are all crammed onto one plane, so getting more means shrinking further. Nanostack stacks transistors 3D along the vertical axis, with upper and lower layers staggered. Within the same footprint, stacking up alone fits more — this is, as far as is known, the industry's first three-dimensional, nanosheet-based transistor architecture.
The stagger isn't arbitrary: offsetting the layers lets connections, heat dissipation, and signal paths route more sensibly between them. IBM's paper at VLSI 2026 covers exactly this — an SRAM cell design built around the "staggered channel."
Not glued together — built up layer by layer through "integration"
The hard part of stacking chips was never the stacking itself — it's getting the layers precisely aligned and actually working. Nanostack uses 3D sequential integration: transistors for the upper layer are integrated directly on top of the already-built lower layer step by step, rather than fabricating two separate dies and bonding them together — so the layers align naturally.
This approach has already been used with ultra-thin dielectric bonding to demonstrate full CMOS integration in experiments — producing not just a design on paper, but a functioning circuit that actually switches on and off correctly. This step is the make-or-break test of whether it can actually be manufactured.
Each stacked layer gets its own optimal material
In a flat architecture, all transistors are forced to share the same materials and process, compromising on each other's behalf. Once stacked into multiple layers, each layer can use a different material combination — upper and lower transistors each pick what suits them best, independently optimizing performance and power without dragging each other down.
This is the extra degree of freedom unlocked by stacking, and why IBM frames it as a "structural plus material" dual innovation: the density gain isn't only from stacking space — the material layering also opens up headroom for performance and efficiency.
Already built and running in the lab
Each of the three experiments demonstrates one thing:
| Validation | What it proves |
|---|---|
| CMOS integration via ultra-thin dielectric bonding | Layers can be joined into a complete CMOS with an ultra-thin dielectric — the stacked structure can actually be built |
| Dual-channel engineering capability | Upper and lower channels in the stacked structure can be controlled simultaneously — multiple layers working together is feasible |
| Functional CMOS inverter | The most basic logic cell switches on and off correctly, with switching performance meeting expectations — not just conducting current |
Separately at VLSI 2026, IBM showed nanostack shrinking SRAM (the chip's high-speed cache) by 40%. Denser SRAM means more cache fits in the same area — which lines up neatly with what advanced AI workloads demand: massive data, high bandwidth. That's a direct line to AI chips.
Who benefits: what 0.7nm actually buys you
This chip is aimed at the compute demands of generative AI, cloud infrastructure, and next-generation electronics. Relative to 2nm, performance and efficiency are an "either/or" trade — depending on how it's tuned, you can't max out both at once. Click below to feel the trade-off.
At the same power draw, it computes faster. For AI, that means the same machine trains and infers with higher throughput, running large models faster.
At the same performance, it's more power-efficient. Power and cooling are already one of the hardest bottlenecks for AI data centers today — this efficiency gain hits that pain point directly.
What the density and efficiency gains mean for two kinds of use cases:
Roughly double the density means nearly double the compute in the same footprint — or, flipped around, the same compute at sharply lower power. AI training and inference costs and cooling today are largely bottlenecked on power, so the efficiency gain is the most valuable part.
Within the same battery and form factor, phones, PCs, and edge devices can run stronger on-device AI models — or stretch battery life further.
Key figures
The figures below are vendor projections or roadmap targets, not measured results:
| Figure | Meaning |
|---|---|
| +50% | Performance gain (vs. 2nm, projected, either/or with efficiency) |
| +70% | Efficiency gain (vs. 2nm, projected, either/or with performance) |
| Within 5 years | IBM's stated production timeline (roadmap) |
| At least 10 years | How much further the process roadmap can keep shrinking |
IBM's process-node history
R&D takes place at the Albany, NY semiconductor research center, and will soon bring in ASML's High-NA EUV lithography systems, with partners including Lam Research, Tokyo Electron, and SCREEN.
We're not just making smaller transistors — we're reinventing how chips are built. Jay Gambetta, Director, IBM Research (IBM press release, 2026-06-25)
Chips used to get stronger by shrinking → this time IBM stacked them up instead
IBM announced the world's first 0.7nm chip, stacking transistors vertically to pack nearly 100 billion of them onto a fingernail-sized die. This page walks through, with diagrams, what it is, how they did it, what it's good for, and which numbers you shouldn't take at face value yet.
↓ Read the whole page · one figure is animated
Start with how chips have gotten stronger. For decades, it's been one playbook: make the transistor — the tiniest switch that turns current on and off — smaller and smaller, so more fit on the same chip, pushing compute and power efficiency up together. The problem: this path is now running out of road.
Instead of grinding harder down the old path, IBM switched direction: if there's no more room on the plane, stack upward. This new build method is called nanostack (a new architecture that stacks transistors vertically layer by layer) — the industry's first genuinely three-dimensional transistor structure.
↑ Hits the atomic wall, nowhere left to shrink
↓ Same footprint, double the count
But stacking chips has always been the hard part — how do you stack precisely, and have it still switch on and off correctly afterward? The diagram below shows how they pulled it off.
Nanostack's key move isn't making transistors smaller — it's redesigning how the chip gets built. There are really just three tricks, tied together in one diagram.
IBM's official figures are "performance up to +50%" and "efficiency up to +70%," but percentages don't mean much on their own. Convert it into how much power the old and new chips each need for the same AI compute job, and the gap becomes real.
more and more packed in
climb together
to a single atom
The new move: nanostack
stacking transistors vertically
3D structure
Does it even switch?
≈2x a 2nm chip
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