Chip Breakthrough · Xiaohu Explains

IBM Unveils World's First 0.7nm Chip, Packing Nearly 100 Billion Transistors Onto a Fingernail-Sized Die

Announced June 25, the node is named 0.7 nanometer (7 angstrom), with density roughly double that of a 2nm chip from four years ago. The core is a new architecture, nanostack, that stacks transistors vertically.
⬡ Semiconductor Milestone · 2026
0.7nm

The world's first sub-1 nanometer logic chip

For over 40 years, chips have advanced by shrinking transistors smaller and smaller — now the size is closing in on a single atom. This is the first time the industry has crossed below 1 nanometer, and IBM's method isn't more shrinking — it's stacking transistors vertically instead.

Nearly 100 billiontransistors on a fingernail-sized chip
≈ 2xdensity vs. a 2nm chip from 4 years ago
+50% / +70%performance OR efficiency (vs. 2nm, projected)
Quick Take
  • IBM announced the world's first sub-1nm chip technology, naming the node 0.7 nanometer (7 angstrom) — a fingernail-sized chip integrating nearly 100 billion transistors, roughly double the density of a 2021 2nm chip.
  • The core innovation is a new transistor architecture called nanostack: instead of shrinking the 2D footprint, transistors are stacked and staggered in 3D — the industry's first three-dimensional nanosheet architecture.
  • Three key techniques: stacking + staggering, 3D sequential integration, and independently optimized materials per layer.
  • Already validated as manufacturable via experiments including a functional CMOS inverter; the +50% performance or +70% efficiency figures are projections relative to 2nm, and it's one or the other, not both.
  • Aimed at generative AI, cloud infrastructure, and next-gen devices; IBM says production could arrive within 5 years, with a roadmap extending at least a decade further.
⚑ This piece is compiled and explained from IBM's official press release. The performance, efficiency, and production-timeline figures are IBM's own projections, not yet validated in mass production.
01

To understand this breakthrough, first see how hard the wall really is

Crossing below 1 nanometer is a milestone because the old path was genuinely running out of road. For decades, chips got better through one straightforward move: make transistors smaller so more fit on the same chip, pushing compute and efficiency up together. The problem is transistor sizes are now approaching the scale of a single atom — there's barely any room left to keep shrinking on a flat plane. The "just make it smaller" path is nearly played out.

Instead of forcing more out of the old path, IBM switched dimensions this time: if there's no more room on the plane, go vertical. Click through the four steps below to see how it doubles transistor count in the same footprint.